View LTC1911_4230778.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3260 1 3260f typical application features description low noise dual supply inverting charge pump the lt c ? 3260 is a low noise dual polarity output power supply that includes an inverting charge pump with both positive and negative ldo regulators. the charge pump operates over a wide 4.5 v to 32 v input range and can deliver up to 100ma of output current. each ldo regulator can provide up to 50ma of output current. the negative ldo post regulator is powered from the charge pump output. the ldo output voltages can be adjusted using external resistor dividers. the charge pump employs either low quiescent current burst mode operation or low noise constant frequency mode. in burst mode operation the charge pump v out regulates to C0.94 ? v in , and the ltc3260 draws only 100a of quiescent current with both ldo regulators on. in constant frequency mode the charge pump produces an output equal to Cv in and operates at a fixed 500khz or to a programmed value between 50khz to 500khz us- ing an external resistor. the ltc3260 is available in low profile (0.75mm) 3mm x 4mm 14- pin dfn and thermally enhanced 16-pin msop packages. 12v outputs from a single 15v input ldo rejection of v out ripple applications n v in range: 4.5v to 32v n inverting charge pump generates Cv in n charge pump output current up to 100ma n low noise negative ldo post regulator ( i ldo C = 50ma max) n low noise independent positive ldo regulator ( i ldo + = 50ma max) n 100 a quiescent current in burst mode ? operation with both ldo regulators on n 50khz to 500khz programmable oscillator frequency n stable with ceramic capacitors n short- circuit/thermal protection n low profile 3mm 4mm 14-pin dfn and thermally enhanced 16-pin msop packages n low noise bipolar/inverting supplies n industrial/instrumentation low noise bias generators n portable medical equipment n portable instruments l, lt , lt c , lt m , burst mode, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 10f 10f 1f 10nf 10nf 10f 10f 909k 909k 200k 100k 100k 12v ?12v 3260 ta01a ldo + 15v ldo ? adj + ltc3260 rt adj ? gnd byp + byp ? v in v out ?15v en + c ? mode en ? c + v ldo + 10mv/div ac-coupled v ldo ? 10mv/div ac-coupled v out 10mv/div ac-coupled 1s/div 3260 ta01b v in = 15v v ldo + = 12v v ldo ? = ?12v f osc = 500khz i ldo + = 50ma i ldo ? ?50ma
ltc3260 2 3260f absolute maximum ratings v in , en + , en C , mode .. ............................... C0.3 v to 36 v ldo + ........................................................... C16 v to 36 v v out , ldo C ............................................... C36 v to 0.3 v rt , adj + ...................................................... C0.3 v to 6 v byp + ......................................................... C0.3 v to 2.5 v adj C ............................................................ C6 v to 0.3 v byp C ......................................................... C2.5 v to 0.3 v (notes 1, 3) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 byp + adj + mode en ? ldo + v in c + en + rt byp ? adj ? ldo ? v out c ? top view 15 gnd de package 14-lead (4mm 3mm) plastic dfn t jmax = 150c, v ja = 43c/w exposed pad (pin 15) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 en + rt byp ? adj ? ldo ? v out c ? nc 16 15 14 13 12 11 10 9 byp + adj + mode en ? ldo + v in c + nc top view mse package 16-lead plastic msop 17 gnd t jmax = 150c, v ja = 43c/w exposed pad (pin 17) is gnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc3260ede#pbf ltc3260ede#trpbf 3260 14-lead (4mm w 3mm) plastic dfn C40c to 125c ltc3260ide#pbf ltc3260ide#trpbf 3260 14-lead (4mm w 3mm) plastic dfn C40c to 125c ltc3260emse#pbf ltc3260emse#trpbf 3260 16-lead plastic msop C40c to 125c ltc3260imse#pbf ltc3260imse#trpbf 3260 16-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ v out , ldo + , ldo C short - circuit duration ........ indefinite operating junction temperature range ( note 2) .................................................. C40 c to 125 c storage temperature range ................. C65 c to 150 c lead temperature ( soldering , 10 sec ) mse only .......................................................... 300 c
ltc3260 3 3260f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = en + = en C = 12v, mode = 0v, rt = 200k. symbol parameter conditions min typ max units charge pump v in input voltage range l 4.5 32 v v uvlo v in undervoltage lockout threshold v in rising v in falling l l 3.4 3.8 3.6 4 v v i vin v in quiescent current shutdown, en + = en C = 0v en C = 0v , i ldo + = 0ma mode = v in , en + = 0v , i vout = i ldo C = 0ma mode = v in , i vout = i ldo + = i ldo C = 0ma mode = 0v , i vout = 0ma 2 30 80 100 3.5 5 50 160 200 5.5 a a a a ma v rt rt regulation voltage 1.200 v v out v out regulation voltage mode = 12v mode = 0v C0.94 ? v in Cv in v v f osc oscillator frequency rt = gnd 450 500 550 khz r out charge pump output impedance mode = 0v , rt = gnd 32 i short _ckt max i vout short- circuit current v out = gnd l 100 160 250 ma v mode(h) mode threshold rising l 1.1 2.0 v v mode(l) mode threshold falling l 0.4 1.0 v i mode mode pin internal pull-down current v in = mode = 32v 0.7 a 50ma positive regulator ldo + output voltage range l 1.2 32 v v adj + adj + reference voltage l 1.176 1.200 1.224 v i adj + adj+ input current v adj + = 1.2v C50 50 na i ldo + (sc) ldo + short- circuit current l 50 100 ma line regulation 0.04 mv /v load regulation 0.03 mv /ma v dropout + ldo + dropout voltage i ldo + = 50ma 400 800 mv output voltage noise c byp + = 10 nf 100 v rms v en + (h) en + threshold rising l 1.1 2.0 v v en + (l) en + threshold falling l 0.4 1.0 v i en + en + pin internal pull-down current v in = en + = 32v 0.7 a 50ma negative regulator ldo C output voltage range l C32 C1.2 v v adj C adj C reference voltage l C1.224 C1.200 C1.176 v i adj C adj C input current v adj C = C1.2v C50 50 na i ldo C (sc) ldo C short- circuit current l 50 100 ma line regulation 0.002 mv /v load regulation 0.02 mv /ma v dropout C ldo C dropout voltage i ldo C = 50ma 200 500 mv output voltage noise c byp C = 10nf 100 v rms v en(h) en C threshold rising l 1.1 2.0 v v en(l) en C threshold falling l 0.4 1.0 v i en C en C pin internal pull-down current v in = en C = 32v 1.4 a
ltc3260 4 3260f typical performance characteristics oscillator frequency vs supply voltage oscillator frequency vs r t shutdown current vs temperature quiescent current vs temperature quiescent current vs supply voltage (constant frequency mode) quiescent current vs temperature (constant frequency mode) (t a = 25c, c f ly = 1f, c in = c out = c ldo + = c ldo C = 10f unless otherwise noted) electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3260 is tested under pulsed load conditions such that t j t a . the ltc3260e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3260i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja = 43c/w is the package thermal impedance. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperatures will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. supply voltage (v) 0 oscillator frequency (khz) 400 500 600 15 25 3260 g01 300 200 5 10 20 30 35 100 0 r t = gnd r t = 200k r t (k) 200 oscillator frequency (khz) 400 600 100 300 500 1 100 1000 10000 3260 g02 0 10 temperature (c) ?50 shutdown current (a) 8 12 150 3260 g03 4 0 0 50 100 ?25 25 75 125 16 6 10 2 14 v in = 32v v in = 12v v in = 5v temperature (c) ?50 quiescent current (a) 80 120 150 3260 g04 40 0 0 50 100 ?25 25 75 125 160 60 100 20 140 burst mode operation with both ldos on positive ldo on burst mode operation with negative ldo on v in = 12v supply voltage (v) 0 quiescent current (ma) 14 15 3260 g05 8 4 5 10 20 2 0 16 12 10 6 25 30 35 f osc = 500khz f osc = 200khz f osc = 50khz temperature (c) ?50 0 quiescent current (ma) 1 3 4 5 10 7 0 50 75 3260 g06 2 8 9 6 ?25 25 100 125 150 f osc = 500khz f osc = 200khz f osc = 50khz v in = 12v
ltc3260 5 3260f typical performance characteristics ldo + gnd pin current vs i load ldo + load regulation adj + pin voltage vs temperature effective open-loop resistance vs supply voltage ldo + dropout voltage vs temperature ldo + supply rejection effective open-loop resistance vs temperature v out short-circuit current vs supply voltage voltage loss (v in C |v out |) vs output current (constant frequency mode) (t a = 25c, c f ly = 1f, c in = c out = c ldo + = c ldo C = 10f unless otherwise noted) supply voltage (v) 0 5 0 v out short-circuit current (ma) 100 250 10 20 25 3260 g08 50 200 150 15 30 35 r t = gnd r t = 200k output current (ma) 0.1 0 voltage loss (v) 2.0 2.5 3.0 f osc = 50khz f osc = 200khz f osc = 500khz 1 10 100 3260 g09 1.5 1.0 0.5 v in = 12v temperature (c) ?50 adj + pin voltage (v) 1.200 1.212 150 3260 g11 1.188 1.176 0 50 100 ?25 25 75 125 1.224 i load (ma) 0 0.08 gnd pin current (ma) 0.10 0.12 0.14 1 10 100 3260 g14 0.06 0.04 0.02 0 v in = 12v supply voltage (v) 0 0 effective open-loop resistance () 10 30 40 50 20 90 3260 g10 20 10 5 25 15 3530 60 70 80 f osc = 200khz f osc = 500khz temperature (c) ?50 0 effective open-loop resistance () 10 20 30 40 0 50 100 150 3620 g07 50 60 ?25 25 75 125 v in = 32v v in = 25v v in = 12v f osc = 500khz temperature (c) ?50 ldo + dropout voltage (mv) 400 600 150 3260 g12 200 0 0 50 100 ?25 25 75 125 800 v in = 12v i ldo + = 50ma 300 500 100 700 frequency (khz) 20 ldo + supply rejection (db) 40 60 10 30 50 0.1 10 100 1000 3260 g13 0 1 v in = 6.5v v ldo + = 5v i ldo + = 50ma v ripple = 50mv rms c ldo + = 10f i ldo + (ma) 0.1 1.1994 v ldo + (v) 1.2002 1.2004 1.2006 1 10 100 3260 g15 1.2000 1.1998 1.1996 v in = 12v unity gain
ltc3260 6 3260f typical performance characteristics ldo + load transient ldo C load transient v out transient (burst mode operation, mode = h) v out transient (mode = low to high) ldo rejection of v out ripple ldo C load regulation (t a = 25c, c f ly = 1f, c in = c out = c ldo + = c ldo C = 10f unless otherwise noted) adj C pin voltage vs temperature ldo C dropout voltage vs temperature ldo C power supply rejection temperature (c) ?50 adj ? pin voltage (v) ?1.200 ?1.188 150 3260 g16 ?1.212 ?1.224 0 50 100 ?25 25 75 125 ?1.176 temperature (c) ?50 ldo ? dropout voltage (mv) 200 300 150 3260 g17 100 0 0 50 100 ?25 25 75 125 400 v out = ?12v i ldo ? = 50ma 150 250 50 350 frequency (khz) 20 ldo ? supply rejection (db) 40 60 10 30 50 0.1 10 100 1000 3260 g18 0 1 v out = ?6.5v v ldo ? = ?5v i ldo ? = ?50ma v ripple = 50mv rms c ldo ? = 10f i ldo ? (ma) 0.1 ?1.2006 v ldo ? (v) ?1.1998 ?1.1996 ?1.1994 1 10 100 3260 g19 ?1.2000 ?1.2002 ?1.2004 v out = ?12v unity gain 1s/div 3260 g20 v ldo + 10mv/div ac-coupled v ldo ? 10mv/div ac-coupled v out 10mv/div ac-coupled v in = 15v v ldo + = 12v v ldo ? = ?12v f osc = 500khz i ldo + = 50ma i ldo ? ?50ma v ldo + 10mv/div ac-coupled i ldo + 40s/div 3260 g21 v in = 12v v ldo + = 5v 20ma 2ma v ldo ? 10mv/div ac-coupled i ldo ? 40s/div 3260 g22 v in = 12v v ldo ? = ?5v refer to figure 3 ?2ma ?20ma v out 500mv/div ac-coupled i out ? 2ms/div 3260 g23 v in = 12v f osc = 500khz ?5ma ?50ma v out 500mv/div ac-coupled 2ms/div 3260 g24 v in = 12v f osc = 500khz i out = ?5ma mode
ltc3260 7 3260f pin functions (dfn/msop) en + ( pin 1/ pin 1): logic input. a logic high on the en + pin enables the positive low dropout (ldo + ) regulator . rt ( pin 2/ pin 2): input connection for programming the switching frequency . the rt pin servos to a fixed 1.2v when the en C pin is driven to a logic high. a resistor from rt to gnd sets the charge pump switching frequency . if the rt pin is tied to gnd , the switching frequency defaults to a fixed 500khz. byp C ( pin 3/ pin 3): ldo C reference bypass pin. connect a capacitor from byp C to gnd to reduce ldo C output noise. leave floating if unused. adj C (pin 4/ pin 4): feedback input for the negative low dropout regulator . this pin servos to a fixed voltage of C1.2v when the control loop is complete. ldo C (pin 5/ pin 5): negative low dropout (ldo C ) linear regulator output. this pin requires a low esr (equivalent series resistance) capacitor with at least 2f capacitance to ground for stability . v out ( pin 6/ pin 6): charge pump output voltage . in constant frequency mode (mode = low) this pin is driven to Cv in . in burst mode operation, (mode = high) this pin voltage is regulated to C0.94 ? v in using an internal burst comparator with hysteretic control. c C (pin 7/ pin 7): flying capacitor negative connection. c + (pin 8/ pin 10): flying capacitor positive connection. nc (pins 8, 9 msop only): no connect. these pins are not connected to the lt c 3260 die. these pins should be left floating, connected to ground or shorted to adjacent pins. v in (pin 9/ pin 11): input voltage for both charge pump and positive low dropout (ldo + ) regulator . v in should be bypassed with a low impedance ceramic capacitor . ldo + (pin 10/ pin 12): positive low dropout (ldo + ) output. this pin requires a low esr capacitor with at least 2f capacitance to ground for stability . en C ( pin 11/ pin 13): logic input. a logic high on the en C pin enables the inverting charge pump as well as the negative ldo regulator . mode (pin 12/ pin 14): logic input. the mode pin deter - mines the charge pump operating mode. a logic high on the mode pin forces the charge pump to operate in burst mode operation regulating v out to approximately C0.94 ? v in with hysteretic control. a logic low on the mode pin forces the charge pump to operate as an open- loop inverter with a constant switching frequency . the switching frequency in both modes is determined by an external resistor from the rt pin to gnd. in burst mode operation , this represents the frequency of the burst cycles before the part enters the low quiescent current sleep state . adj + (pin 13/ pin 15): feedback input for the positive low dropout (ldo + ) regulator . this pin servos to a fixed voltage of 1.2v when the control loop is complete. byp + (pin 14/pin 16): ldo + reference bypass pin. con- nect a capacitor from byp + to gnd to reduce ldo + output noise. leave floating if unused. gnd (exposed pad pin 15/ exposed pad pin 17): ground. the exposed package pad is ground and must be soldered to the pc board ground plane for proper functionality and for rated thermal performance.
ltc3260 8 3260f block diagram note: pin numbers are as per dfn package. refer to the pin functions section for corresponding msop pin numbers. 9 10 13 14 ? + ? + 1.2v ref inverting charge pump ?1.2v ref charge pump and input logic 50khz to 500khz osc ldo + en + v in c + s1 s4 s3 adj + byp + 3 4 byp ? adj ? 5 15 ldo ? gnd 1 8 c ? s2 7 rt 2 en ? 11 mode 12 v out 6 operation (refer to the block diagram) the ltc3260 is a high voltage low noise dual output regulator. it includes an inverting charge pump and two ldo regulators to generate bipolar low noise supply rails from a single positive input. it supports a wide input power supply range from 4.5v to 32v. shutdown mode in shutdown mode, all circuitry except the internal bias is turned off. the ltc3260 is in shutdown when a logic low is applied to both the enable inputs (en + and en C ). the ltc3260 only draws 2a (typical) from the v in supply in shutdown. charge pump constant frequency operation the ltc3260 provides low noise constant frequency op- eration when a logic low is applied to the mode pin. the charge pump and oscillator circuit are enabled using the en C pin. at the beginning of a clock cycle, switches s1 and s2 are closed. the external flying capacitor across the c + and c C pins is charged to the v in supply. in the second phase of the clock cycle, switches s1 and s2 are opened, while switches s3 and s4 are closed. in this configuration the c + side of the flying capacitor is grounded and charge is delivered through the c C pin to v out . in steady state the v out pin regulates at Cv in less any voltage drop due to the load current on v out or ldo.
ltc3260 9 3260f operation (refer to the block diagram) figure 1. oscillator frequency vs r t the charge transfer frequency can be adjusted between 50khz and 500khz using an external resistor on the rt pin. at slower frequencies the effective open-loop output resistance (r ol ) of the charge pump is larger and it is able to provide smaller average output current (see the available output current vs f osc graph in the typical per - formance characteristics section). figure 1 can be used to determine a suitable value of rt to achieve a required oscillator frequency. if the rt pin is grounded, the part operates at a constant frequency of 500khz. r t (k) 200 oscillator frequency (khz) 400 600 100 300 500 1 100 1000 10000 3260 f01 0 10 charge pump burst mode operation the ltc3260 provides low power burst mode operation when a logic high is applied to the mode pin. in burst mode operation, the charge pump charges the v out pin to C0.94 ? v in (typical). the part then shuts down the internal oscillator to reduce switching losses and goes into a low current state. this state is referred to as the sleep state in which the ic consumes only about 100a with both ldos enabled. when the output voltage droops enough to over - come the burst comparator hysteresis, the part wakes up and commences charge pump cycles until output voltage exceeds C0.94 ? v in (typical). this mode provides lower operating current at the cost of higher output ripple and is ideal for light load operation. the frequency of charging cycles is set by the external resistor on the rt pin. the charge pump has a lower r ol at higher frequencies. for burst mode operation it is recommended that the rt pin be tied to gnd. this mini- mizes the charge pump r ol , quickly charges the output up to the burst threshold and optimizes the duration of the low current sleep state. charge pump soft-start the ltc3260 has built in soft-start circuitry to prevent excessive current flow during start-up. the soft-start is achieved by internal circuitry that slowly ramps the amount of current available at the output storage capacitor. the soft-start circuitry is reset in the event of a commanded shutdown or thermal shutdown. charge pump short-circuit/thermal protection the ltc3260 has built-in short- circuit current limit as well as overtemperature protection. during a short- circuit condition, the part automatically limits its output current to approximately 160ma. if the junction temperature exceeds approximately 175 c the thermal shutdown circuitry disables current delivery to the output. once the junction temperature drops back to approximately 165c current delivery to the output is resumed. when thermal protection is active the junction temperature is beyond the specified operating range. thermal protection is intended for momentary overload conditions outside normal operation. continuous operation above the speci- fied maximum operating junction temperature may impair device reliability. positive low dropout linear regulator (ldo + ) the positive low dropout regulator (ldo + ) supports a load of up to 50ma. the ldo + takes power from the v in pin and drives the ldo + output pin to a voltage programmed by the resistor divider connected between the ldo + , adj + and gnd pins. for stability, the ldo + output must be by- passed to ground with a low esr ceramic capacitor that maintains a capacitance of at least 2f across operating temperature and voltage. the ldo + is enabled or disabled via the en + logic input pin. when the ldo + is enabled, a soft-start circuit ramps its regulation point from zero to the final value over a period of 75s, reducing the inrush current on v in .
ltc3260 10 3260f operation (refer to the block diagram) figure 2 shows the ldo + regulator application circuit . the ldo + output voltage v ldo + can be programmed by choosing suitable values of r1 and r2 such that: v ldo + = 1.2v ? r1 r2 + 1 ? ? ? ? ? ? an optional capacitor of 10nf can be connected from the byp + pin to ground. this capacitor bypasses the internal 1.2v reference of the ltc3260 and improves the noise performance of the ldo + . if this function is not used the byp + pin should be left floating. negative by the charge pump circuitry . soft-start circuitry in the charge pump also provides soft-start functionality for the ldo C and prevents excessive inrush currents. figure 3 shows the ldo C regulator application circuit . the ldo C output voltage v ldo C can be programmed by choosing suitable values of r1 and r2 such that: v ldo ? = ?1.2v ? r1 r2 + 1 ? ? ? ? ? ? when the inverting charge pump is in burst mode opera- tion (mode = high), the typical hysteresis on the v out pin is 2% of v in voltage. the ldo C voltage should be set high enough above v out in order to prevent ldo C from entering dropout during normal operation. an optional capacitor of 10nf can be connected from the byp C pin to ground. this capacitor bypasses the internal C1.2v reference of the ltc3260 and improves the noise performance of the ldo C . if this function is not used the byp C pin should be left floating. in order to improve transient response , an optional capacitor, c adj C , may be used as shown in figure 3. a recommended value for c adj C is 10pf. experimentation with capacitor values between 2pf and 22pf may yield improved transient response. figure 2: positive ldo application circuit v in 1 0 ldo + en + adj + gnd byp + c byp + c out ltc3260 ldo output r2 3260 f02 r1 1.2v ref figure 3: negative ldo application circuit v out 1 0 ldo ? en ? adj ? gnd byp ? c byp ? c adj ? c out 3260 f03 ltc3260 ldo output r2 r1 ?1.2v ref negative low dropout linear regulator (ldo C ) the negative low dropout regulator (ldo C ) supports a load of up to 50ma. the ldo C takes power from the v out pin (output of the inverting charge pump) and drives the ldo C output pin to a voltage programmed by the resis- tor divider connected between the ldo C , adj C and gnd pins. for stability, the ldo C output must be bypassed to ground with a low esr ceramic capacitor that maintains a capacitance of at least 2f across operating temperature and voltage. the ldo C is enabled or disabled via the en C logic input pin. initially, when the en C logic input is low, the charge pump circuitry is disabled and the v out pin is at gnd. when en C is switched high, the v out pin will be driven
ltc3260 11 3260f applications information effective open-loop output resistance the effective open - loop output resistance ( r ol ) of a charge pump is a very important parameter which determines the strength of the charge pump. the value of this parameter depends on many factors such as the oscillator frequency (f osc ), value of the flying capacitor (c f ly ), the nonoverlap time, the internal switch resistances (r s ) and the esr of the external capacitors. typical r ol values as a function of temperature are shown in figure 4 minimum turn-on time. the peak-to-peak output ripple at the v out pin is approximately given by the expression: v ripple(p-p) i out c out 1 f osc ? t on ? ? ? ? ? ? where c out is the value of the output capacitor, f osc is the oscillator frequency and t on is the on-time of the oscillator (1s typical). just as the value of c out controls the amount of output ripple , the value of c in controls the amount of ripple present at the input (v in ) pin. the amount of bypass capacitance required at the input depends on the source impedance driving v in . for best results it is recommended that v in be bypassed with at least 2f of low esr capacitance. a high esr capacitor such as tantalum or aluminum will have higher input noise than a low esr ceramic capacitor. therefore, a ceramic capacitor is recommended as the main bypass capacitance with a tantalum or aluminum capacitor used in parallel if desired. flying capacitor selection the flying capacitor controls the strength of the charge pump. a 1f or greater ceramic capacitor is suggested for the flying capacitor for applications requiring the full rated output current of the charge pump. for very light load applications, the flying capacitor may be reduced to save space or cost. for example, a 0.2f capacitor might be sufficient for load currents up to 20ma. a smaller flying capacitor leads to a larger effective open- loop resistance (r ol ) and thus limits the maximum load current that can be delivered by the charge pump. ceramic capacitors ceramic capacitors of different materials lose their capaci- tance with higher temperature and voltage at different rates. for example, a capacitor made of x5r or x7r material will retain most of its capacitance from C40c to 85c whereas a z 5 u or y 5 v style capacitor will lose considerable capacitance over that range. z5u and y5v capacitors may figure 4. typical r ol vs temperature input/output capacitor selection the style and value of capacitors used with the ltc3260 determine several important parameters such as regulator control loop stability, output ripple, charge pump strength and minimum turn-on time. to reduce noise and ripple, it is recommended that low esr ceramic capacitors be used for the charge pump and ldo outputs. all capacitors should retain at least 2f of capacitance over operating temperature and bias voltage. tantalum and aluminum capacitors can be used in parallel with a ceramic capacitor to increase the total capacitance but should not be used alone because of their high esr. in constant frequency mode, the value of c out directly controls the amount of output ripple for a given load current. increasing the size of c out will reduce the output ripple at the expense of higher temperature (c) ?50 0 effective open-loop resistance () 10 20 30 40 0 50 100 150 3620 f04 50 60 ?25 25 75 125 v in = 32v v in = 25v v in = 12v f osc = 500khz
ltc3260 12 3260f applications information also have a poor voltage coefficient causing them to lose 60% or more of their capacitance when the rated voltage is applied . therefore when comparing different capacitors , it is often more appropriate to compare the amount of achievable capacitance for a given case size rather than discussing the specified capacitance value. the capacitor manufactures data sheet should be consulted to ensure the desired capacitance at all temperatures and voltages. table 1 is a list of ceramic capacitor manufacturers and their websites. table 1 avx www.avxcorp.com kemet www.kemet.com murata www.murata.com taiyo yuden www.t-yuden.com vishay www.vishay.com tdk www.component.tdk.com layout considerations due to high switching frequency and high transient currents produced by ltc3260, careful board layout is necessary for optimum performance . a true ground plane and short connections to all the external capacitors will improve performance and ensure proper regulation under all condi- tions. figure 5 shows an example layout for the ltc3260. the flying capacitor nodes c + and c C switch large cur - rents at a high frequency. these nodes should not be routed close to sensitive pins such as the ldo feedback pins (adj + and adj C ) and internal reference bypass pins (byp + and byp C ). thermal management at high input voltages and maximum output current, there can be substantial power dissipation in the ltc3260. if the junction temperature increases above approximately 175c, the thermal shutdown circuitry will automatically deactivate the output. to reduce the maximum junction temperature, a good thermal connection to the pc board ground plane is recommended . connecting the exposed pad of the package to a ground plane under the device on two layers of the pc board can reduce the thermal resistance of the package and pc board considerably. derating power at high temperatures to prevent an overtemperature condition in high power applications, figure 6 should be used to determine the maximum combination of ambient temperature and power dissipation. the power dissipated in the ltc3260 should always fall under the line shown for a given ambient temperature. the power dissipated in the ltc3260 has three components. power dissipated in the positive ldo: p ldo + = (v in C v ldo + ) ? i ldo + power dissipated in the negative ldo: p ldo C = (|v out | C |v ldo C |) ? i ldo C and power dissipated in the inverting charge pump: p cp = (v in C |v out |) ? (i out + i ldo C ) where i out denotes any additional current that might be pulled directly from the v out pin. the ldo C current is also supplied by the charge pump through v out and is therefore included in the charge pump power dissipation. the total power dissipation of the ltc3260 is given by: p d = p ldo + + p ldo C + p cp figure 5. recommended layout v out v in ldo ? ldo + gnd 3260 f05 c byp + c f ly gnd c byp ? r t
ltc3260 13 3260f applications information the derating curve in figure 6 assumes a maximum thermal resistance, ja , of 43c/w for the package. this can be achieved from a printed circuit board layout with a solid ground plane and a good connection to the exposed pad of the ltc3260 package. it is recommended that the ltc3260 be operated in the region corresponding to t j 150c for continuous opera- tion as shown in figure 6. short-term operation may be acceptable for 150c < t j < 175 c but long-term operation in this region should be avoided as it may reduce the life of the part or cause degraded performance . for t j > 175c the part will be in thermal shutdown. figure 6. maximum power dissipation vs ambient temperature typical applications low power 24v power supply from a single-ended 28v input supply c4 4.7f c1 4.7f c2 1f c7 4.7f c3 4.7f r4 1.91m r1 1.91m r3 100k r2 100k 24v ?24v 3260 ta02 ldo + 9 1 11 12 8 7 6 2 5 4 3 15 14 13 10 28v ldo ? adj + ltc3260 rt adj ? gnd byp + byp ? v in v out en + c ? mode en ? c + high voltage input to bipolar output with highly efficient dividing/inverting charge pump c1 4.7f 50v c4 4.7f c8 4.7f 25v c7 4.7f c6 0.01f c5 0.01f c2 1f 50v c3 1f 50v note: the ltc3260 will always run in continuous frequency regardless of the mode pin setting because v out is always less than ?1/2v in d1 mbr0540 d2 mbr0540 d3 mbr0540 14 17 2 r1 316k r2 100k r3 100k r4 316k 5v ?5v 3260 ta04 ldo + 11 12 15 16 3 4 5 13 10 7 1 13.5v to 32v ldo ? 6 v out adj + ltc3260 gnd rt mode adj ? byp + byp ? v in en + c ? en ? c + v out ~ ? v in ? v f ? i out ? rol 2 ? v f ? ? ? ? ? ? ambient temperature (c) ?50 0 maximum power dissipation (w) 1 3 4 5 0 50 75 175 3260 f06 2 ?25 25 100 125 150 6 thermal shutdown recommended operation t j = 150c t j = 175c ja = 43c/w
ltc3260 14 3260f typical applications 28v dual tracking bipolar supply with outputs from 5v to 25v c1 4.7f 50v c3 4.7f 35v c7 4.7f 50v c6 4.7f 35v c4 0.01f c2 1f 50v 14 2 17 r1 732k r2 73.2k r3 500k r4 732k out ?out 3260 ta05 ldo + 11 12 15 16 4 3 5 13 10 7 1 28v ldo ? 6 v out adj + ltc3260 gnd mode rt adj ? byp + byp ? v in en + c ? en ? c + c5 0.01f package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 3.30 0.10 1.70 0.05 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 3.30 0.05 0.50 bsc de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b)
ltc3260 15 3260f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (mse16) 0911 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev e)
ltc3260 16 3260f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0412 ? printed in usa related parts typical application low noise 12v power supply from a single-ended 15v input supply (frequency = 200khz) c4 10f c5 10nf c6 10nf c1 10f c2 1f c7 10f c3 10f r4 909k r5 200k r1 909k r3 100k r2 100k 12v ?12v 3260 ta03 ldo + 9 1 11 12 8 7 6 2 5 4 3 15 14 13 10 15v ldo ? adj + ltc3260 rt adj ? gnd byp + byp ? v in v out en + c ? mode en ? c + part number description comments ltc1144 switched-capacitor wide input range voltage converter with shutdown wide input voltage range: 2v to 18v, i sd < 8a, so8 package ltc1514/ltc1515 step-up/step-down switched-capacitor dc/dc converters v in : 2v to 10v, v out : 3.3v to 5v, i q = 60a, so8 package lt ? 1611 150ma output, 1.4mhz micropower inverting switching regulator v in : 0.9v to 10v, v out = 34v, thinsot? package lt1614 250ma output, 600khz micropower inverting switching regulator v in : 0.9v to 6v, v out = 30v, i q = 1ma, ms8, so8 packages LTC1911 250ma, 1.5mhz inductorless step-down dc/dc converter v in : 2.7v to 5.5v, v out = 1.5v/1.8v, i q = 180a, ms8 package ltc3250/ltc3250-1.2/ ltc3250-1.5 inductorless step-down dc/dc converters v in : 3.1v to 5.5v, v out = 1.2v, 1.5v, i q = 35a, thinsot package ltc3251 500ma spread spectrum inductorless step-down dc/dc converter v in : 2.7v to 5.5v, v out : 0.9v to 1.6v, 1.2v, 1.5v, i q = 9a, ms10e package ltc3252 dual 250ma, spread spectrum inductorless step-down dc/dc converter v in : 2.7v to 5.5v, v out : 0.9v to 1.6v, i q = 50a, dfn12 package lt1054/lt1054l switched-capacitor voltage converters with regulator v in : 3.5v to 15v/7v, i out = 100ma/125ma, n8, s08, so16 packages

▲Up To Search▲

Price & Availability of LTC1911

	To Download LTC1911 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .